This invention relates to dynamic memories and more particularly to refresh circuitry used in such memories.
As is known in the art, dynamic memories, such as Dynamic Random Access Memories (DRAMs) for example, require that the data stored therein be refreshed from time to time. In the case of a DRAM, an array of memory cells is provided on an integrated circuit chip. A typical memory cells includes a transistor coupled to a storage element, typically a capacitor. Each cell stores a bit (i.e., a logic 1 or a logic 0) of the data. The cells are arranged in a matrix of addressable rows and columns, with each row corresponding to a multi-bit word of data. The bit of data in each cell is stored on the capacitor as a charge, or lack thereof. This data must be refreshed because the charge of the capacitor leaks therefrom over time, i.e., over the charge, or data retention time of the cell. In order to prevent the loss of data, the data stored in the cell must be refreshed before the end of the data retention time. It follows then that the faster the charge leaks from the cell, the higher the data refresh rate required for the cell.
Generally, the power consumption used during a data refresh cycle is relatively high. Thus, it is descried to have cells with high data retention times.
One technique used to determine the data refresh rate for a memory array is to use an external (i.e., off-chip) tester. The tester measures the data retention time of each of the memory cells in the array. A minimum data retention time is thus determined by the xe2x80x9cweakestxe2x80x9d of all the memory cells (i.e., the cell with the shortest data retention time). If this data retention time is below a specified value, these xe2x80x9cweakxe2x80x9d cells cannot be used and may, be replaced with redundancy cells, if they are available. Otherwise, the chip must be discarded thereby reducing yield and increasing product cost.
One typical DRAM is shown in FIG. 1. Thus, in this example, the memory array includes four banks of memory cells refreshed by a refresh circuit. The refresh circuit includes a counter for supplying row addresses to the memory cells in response to refresh commands supplied externally of the chip. Thus, the DRAM includes an internal, i.e., on-chip, refresh counter which supplies the row address of the word line that is to be refreshed with the next external refresh command. The counter either starts from an arbitrary row address or is preset to some initial value. After the counter reaches its maximum value, it wraps around and restarts with its minimum value. The counter value is incremented wit=h each external refresh command.
Another refresh system is described in U.S. Pat. No. 5,857,143 entitled xe2x80x9cDynamic Memory Device With Refresh Circuit and Refresh Methodxe2x80x9d, inventor Ben-Zvi, issued Feb. 23, 1999. Here, the memory array can be refreshed partially to reduce energy consumption. Still another refresh circuit is described in U.S. Pat. No. 5,331,601 entitled xe2x80x9cDRAM Variable Row Selectxe2x80x9d inventor Parris, issued Jul. 19, 1994. Here a memory device alters the input refresh addresses to fewer memory cells to save power, or to address more memory cells to decrease refresh time.
In accordance with the present invention, a refresh circuit is provided for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh command signal along with refresh addresses to the array of memory cells. The cells have data stored therein in response to the internal refresh command signals, such refreshed cells being addressed by the refresh addresses.
With such an arrangement, power consumption and/or yield may be increased.
In one embodiment, the refresh rate analysis circuit is formed on the chip.
In accordance with one embodiment, the refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value. The refresh address generator generates the internal refresh commands at a first rate for the memory cells having retention times greater than such predetermined value and the internal refresh commands at a second lower rate for cells having retention times greater that such predetermined value.
In one embodiment, the refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value. The refresh address generator generates internal refresh commands and refresh addresses during a first cycle and a during a subsequent second cycle. During the first cycle the memory cells in the array are supplied the internal refresh commands and wherein during the second cycle only a fractional portion of the cells in such array are supplied the internal refresh commands.
With such embodiment, power is saved since during the second cycle cells with higher data retention times are not refreshed.
In one embodiment, the refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value. The refresh address generator generates internal refresh commands during a first cycle and a during a subsequent second cycle. During the first cycle the memory cells in the array are supplied internal refresh commands and wherein during the second cycle the same one of the cells in such array is supplied a plurality of refresh commands.
With such embodiment, the first and second cycles are initiated in response to each externally generated refresh command. Yet, yield is improved because cells having data retention times less than the time external refresh commands are supplied are able to be retained and not discarded because they are refreshed more than once during the second refresh cycle.
In one embodiment, the refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value. The refresh address generator generates internal refresh commands during a first cycle and a during a subsequent second cycle. During each one of the first and second cycles the refresh address generators generates a plurality of the internal refresh commands. During the first cycle the memory cells in the array are each supplied a corresponding one of the plurality of internal refresh commands. During the second cycle one of the cells in such array is supplied a more than one of the plurality of the internal refresh commands and another one of the cells is inhibited from being supplied at least one of the plurality of the internal refresh commands.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.